1. Field of the Invention
The present invention relates to a static random access memory in which each memory cell comprises a flip-flop and access transistors.
2. Description of the Prior Art
Static semiconductor memories (SRAM) in which each memory cell comprises a flip-flop and access transistors have been widely used in general information processing systems since they have less restrictions on operation and short access time.
Referring now to FIG. 1, there is shown a circuit diagram showing a prior art static memory cell. The memory cell comprises pairs of a resistor 3 and an nMOS transistor 1 and a resistor 4 and an nMOS transistor 2. Each pair of the resistor and the nMOS transistor forms an inverter and is connected in series between a power source voltage Vcc and a ground voltage GND. The resistors 3 and 4 and the nMOS transistors 1 and 2 form a flip-flop. The drain of each of the nMOS transistors 1 and 2 is a memory node. The drain of the nMOS transistor is connected with a bit line BL1 via an nMOS transistor 5 which is an access transistor. The drain of the nMOS transistor 2 is connected with a bit 11he BL2 via an nMOS transistor 6 which is an access transistor.
Referring now to FIG. 2, there is shown a layout on a chip, the circuit of which is shown in FIG. 1. The word line, which is marked WL in FIG. 1, is comprised of a polysilicon layer 7 and the gate electrodes of the drive transistors 1 and 2 are comprised of polysilicon layers 8a and 8b. On this layout, the gate length L.sub.AC of the access transistor and the gate width W.sub.OR of the drive transistor determined the cell size in a Y direction of the drawing and the gate length L.sub.DR of the drive transistor and the gate width W.sub.AC of the access transistor determine the cell size in an X direction of the drawing. The source/drain region of each transistor is formed by a gate electrode and a field oxide film (formed by LOCOS process) by a self-alignment technique.
However, the semiconductor memory having the above-mentioned structure is difficult to achieve in high density integration and is disadvantageous in terms of consumed current and data holding capability.
In order to provide a high data holding ability on reading data and a high noise margin, it is necessary to provide a high memory cell ratio .beta..sub.DR /.beta..sub.AC (=W.sub.DR L.sub.AC /W.sub.AC L.sub.DR). In order to provide a high memory cell ratio, it is necessary to preset the size of a memory cell so that the gate width W.sub.DR and the gate length L.sub.AC are increased and the gate width W.sub.AC and the gate length L.sub.DR are decreased. As is apparent from FIG. 2, both the gate width W.sub.DR of the drive transistors and the gate length of the access transistor are of a greater size in the Y-direction. Accordingly, if they are increased to provide a high ratio, the cell size cannot be decreased. High density integration would become difficult.
If the supplied power source voltage Vcc is less, consumed power is less and high density integration is possible. However, in the memory cell having the above-mentioned structure, the minimum operating power source voltage Vccmin is determined by a sum of Vth.sub.DR (threshold voltage of the drive transistor) , Vth.sub.AC (threshold voltage of the access transistor) and .DELTA.Vth.sub.AC (a substrate effect of the threshold voltage of the access transistor). The Vth.sub.AC is preset high in order to provide a high memory cell ratio. The gate width W.sub.AC is minimized. Accordingly, .DELTA.Vth.sub.AC is made relatively high by a narrow channel effect. Therefore, lower minimum operation power source voltages cannot be used and the potential at the memory node is lowered, resulting in difficulty in improving soft error immunity.